{"id":82259,"date":"2025-03-27T03:00:55","date_gmt":"2025-03-27T10:00:55","guid":{"rendered":"https:\/\/www.jamasoftware.com\/?p=82259"},"modified":"2025-03-27T10:12:23","modified_gmt":"2025-03-27T17:12:23","slug":"synopsys-bold-prediction-50-of-new-hpc-chip-designs-will-be-multi-die-in-2025","status":"publish","type":"post","link":"https:\/\/www.jamasoftware.com\/legacy\/blog\/2025\/03\/27\/synopsys-bold-prediction-50-of-new-hpc-chip-designs-will-be-multi-die-in-2025\/","title":{"rendered":"Synopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025"},"content":{"rendered":"
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Jama Software is always looking for news that would benefit and inform our industry partners. As such, we\u2019ve curated a series of customer and industry spotlight articles that we found insightful. In this blog post, we share an article from Synopsys\u00ae<\/sup><\/a>, titled \u201cSynopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025\u201d,<\/a> and written by Michael Posner<\/a> and Shekhar Kapoor<\/a> and published on January 21, 2025.<\/p><\/div>\n

Synopsys Bold Prediction: 50% of New HPC Chip Designs Will Be Multi-Die in 2025<\/h2>\n

Monolithic chips have been the workhorses behind decades of technological advancement. But just as the industrial revolution saw workhorses replaced with more efficient and powerful machinery, the semiconductor industry is on the cusp of a similar revolution.<\/p>\n

Multi-die and chiplet-based designs \u2014 which integrate multiple specialized dies in a single package or stack integrated circuits vertically \u2014 stand to deliver far greater performance and flexibility than monolithic chips, capable of supporting the insatiable processing demands of high-performance computing (HPC) and AI-driven workloads. But pursuing these advanced chip designs has required the deepest of pockets and most advanced R&D capabilities.<\/p>\n

Until now.<\/p>\n

Multi-die technologies, tools, flows, and IP have matured rapidly. Engineering expertise has evolved. And foundry capacity continues to expand. With this in mind, we predict 50% of new HPC chip designs will be 2.5D or 3D multi-die in 2025.<\/p>\n

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Foundries preparing for wave of 2.5D and 3D multi-die designs<\/h3>\n

It takes more than R&D to bring 2.5D and 3D multi-die designs to market. It also requires high-bandwidth, low-latency interconnects (3DIO), advanced manufacturing processes with sufficient capacity, and sophisticated design tools and IP.<\/p>\n

Open industry standards like UCIe (Universal Chiplet Interconnect Express) continue to mature, helping simplify and strengthen the connectivity between heterogeneous chiplets while reducing risk and accelerating design cycles. The increased adoption of UCIe for HPC, AI, data center, and edge applications is driving significant demand for 2.5D and 3D multi-die designs.<\/p>\n

In addition to the maturation and proliferation of advanced interconnects, foundries are preparing for the oncoming wave of 2.5D and 3D multi-die designs. This includes new manufacturing processes that offer denser bumps and higher performance. Additional package, interposer, and integration options provide cost and architectural flexibility. And expanded production capacity means more designs and prototypes can be brought to market.<\/p>\n

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Advanced multi-die design tools and IP<\/h3>\n

Developing these cutting-edge chips would not be possible without the most advanced design solutions, and Synopsys remains at the forefront of 2.5D and 3D multi-die innovation. Our comprehensive and scalable multi-die solutions<\/a>, including design automation tools and IP, enable:<\/p>\n